Lead ASIC Verification Engineers [Ref:102]

at Sivaltech
Location San Diego, California
Date Posted July 30, 2022
Category Engineering
Job Type Not Specified


Requirement details:

  • Write Functional and code coverage, digital design and verification of all areas of lifecycle
  • Plan and debug tests
  • h4 Development of test cases, checkers, and scoreboards
  • Develop a complete test bench in System Verilog with Universal Verification Methodology (UVM)
  • Work on simulators like Verilog Compiler Simulator (VCS)
  • Plan for Assertion, Coverage metrics and coverage closure to make sure designs are verified thoroughly
  • Digital Design and Verification (ASIC & RTL)
  • Work on modem processors and protocols like AHB, AXI and perform design verification on all areas of verification lifecycle
  • Tools:

  • UVM Methodology, Verilog, System Verilog
  • Minimum Education :

  • Master's degree in Electronics / Electrical Engineering Technology
  • Minimum experience :

  • Two (2) years Two (2) years of experience must include two (2) years of experience in: UVM Methodology, Verilog, System Verilog. Employer will conduct background check and reference check
  • Job Site :

  • San Diego, CA. Job may involve working at various unanticipated locations throughout the United States. Travel required to the extent of relocating to various unanticipated locations throughout the United States. Please send resumes referencing the aforementioned job title and reference number to Sivaltech Inc. 6170 Cornerstone Ct. E, Ste 260, San Diego CA 92121
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