Principal RF/MS Clocking / PLL Design Engineer

at MaxLinear
Location Irvine, California
Date Posted July 31, 2022
Category Engineering
Job Type Not Specified

Description

Responsibilities

MaxLinear is seeking a Principal RF/MS IC Design Engineer with background in Clocking / PLLs to join our growing team. You will work closely with a world-class team of IC designers to design high-performance ICs with RF, analog, mixed-signal and digital systems integrated on a single chip.

The team drives architecture / topology selection, design, implementation, and verification of RF/mixed-signal systems that include circuit blocks such as LNAs, Mixers, PAs, PLLs, VCOs, ADCs, DACs. In this role, you will focus on the following:

  • Responsible of clocking IP on SOCs including Analog or Digital PLLs, Clock Distribution
  • Provide technical leadership and mentorship of engineers working on IP
  • Collaborate with system engineers to optimize circuit designs and system specification trade-offs
  • Report the results of IC design, analysis, and evaluation

    • Qualifications

  • Strong background, product experience in Analog/Digital PLLs, Clocking in CMOS
  • Solid understanding of CMOS process and device physics
  • Strong written and verbal communication skills required

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