Senior Engineer

Location Austin, Texas
Date Posted July 31, 2022
Category Engineering
Job Type Not Specified


Position Summary

Samsung is a world leader in Memory, LCD and System LSI technologies. We are currently looking for exceptional software and hardware talent to join our Samsung Austin R & D Center (SARC) in Austin, TX and our Advanced Computing Lab (ACL) in San Jose, CA. SARC was established in Austin, TX in 2010 to be one of Samsung s strategic investments in high performance low power ARM based device technology. Presently our GPU design teams, located in Austin (SARC) and San Jose (ACL), are developing a GPU that will be deployed in Samsung mobile products. Our System IP team located in Austin (SARC) is working on Coherent Interconnect and memory controller architectures.

Role and Responsibilities

As a Timing Engineer you will have responsibility for top level timing constraints generation/debug on complex GPU/SOCs including configuring different timing modes (Func, DFT, JTAG, MBIST, etc).

Role and Responsibilities:

  • Work with a team of engineers on timing closure and constraints generation/debug.
  • Understanding of different implementation styles of clock in design and latency/skew.
  • Understanding of clock domain crossings, source synchronous buses, multi-voltage timing.
  • Understanding of timing sign off flow and methodology, timing budgeting, derating and timing across different voltage domains.
  • Working knowledge of special timing checks (Asynchronous, source sync interfaces, etc).
  • Interact with RTL and SOC physical implementation teams to resolve timing issues.
  • Mentoring junior engineers in different areas of timing flows and methodologies.
  • Ability to influence flow and methodology enhancements for improvement.
  • Ability to work independently and influence cross functional teams to make good technical design trade-offs between power, area, and timing.
  • Skills and Qualifications

    Minimum Requirements:

  • BSEE with 4+ years relevant experience (or equivalent education and demonstrated work experience).
  • Strong communication skills, team player working in collaborative work environment, discipline and planning; ability to execute with high quality deliverables is a must.
  • Understanding and working knowledge of the SOC/ASIC design flow.
  • Possesses strong technical qualities and skillsets with good analytical debug skills.
  • Experience with smaller process nodes is strongly preferred.
  • Working knowledge and detail understanding of OCV, AOCV & POCV is preferred.
  • Strong hands-on experience with industry standard STA tools (Ex. PrimeTime, Tempus).
  • Hands-on experience with synthesis, block and/or full chip implementation with the latest industry P&R/STA flows and tools an added plus.
  • Experience with clock tree synthesis (CTS), multi-voltage and multi-clock designs is a plus.
  • Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure is an added advantage.
  • Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python is preferred.
  • Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to details.
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